mx6s_capture.c 56.3 KB
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/*
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 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved.
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 */

/*
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/*!
 * @file mx6s_csi.c
 *
 * @brief mx6sx CMOS Sensor interface functions
 *
 * @ingroup CSI
 */
#include <asm/dma.h>
#include <linux/busfreq-imx.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/gcd.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/mfd/syscon.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/media-bus-format.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>

#define MX6S_CAM_DRV_NAME "mx6s-csi"
#define MX6S_CAM_VERSION "0.0.1"
#define MX6S_CAM_DRIVER_DESCRIPTION "i.MX6S_CSI"

#define MAX_VIDEO_MEM 64

/* reset values */
#define CSICR1_RESET_VAL	0x40000800
#define CSICR2_RESET_VAL	0x0
#define CSICR3_RESET_VAL	0x0

/* csi control reg 1 */
#define BIT_SWAP16_EN		(0x1 << 31)
#define BIT_EXT_VSYNC		(0x1 << 30)
#define BIT_EOF_INT_EN		(0x1 << 29)
#define BIT_PRP_IF_EN		(0x1 << 28)
#define BIT_CCIR_MODE		(0x1 << 27)
#define BIT_COF_INT_EN		(0x1 << 26)
#define BIT_SF_OR_INTEN		(0x1 << 25)
#define BIT_RF_OR_INTEN		(0x1 << 24)
#define BIT_SFF_DMA_DONE_INTEN  (0x1 << 22)
#define BIT_STATFF_INTEN	(0x1 << 21)
#define BIT_FB2_DMA_DONE_INTEN  (0x1 << 20)
#define BIT_FB1_DMA_DONE_INTEN  (0x1 << 19)
#define BIT_RXFF_INTEN		(0x1 << 18)
#define BIT_SOF_POL		(0x1 << 17)
#define BIT_SOF_INTEN		(0x1 << 16)
#define BIT_MCLKDIV		(0xF << 12)
#define BIT_HSYNC_POL		(0x1 << 11)
#define BIT_CCIR_EN		(0x1 << 10)
#define BIT_MCLKEN		(0x1 << 9)
#define BIT_FCC			(0x1 << 8)
#define BIT_PACK_DIR		(0x1 << 7)
#define BIT_CLR_STATFIFO	(0x1 << 6)
#define BIT_CLR_RXFIFO		(0x1 << 5)
#define BIT_GCLK_MODE		(0x1 << 4)
#define BIT_INV_DATA		(0x1 << 3)
#define BIT_INV_PCLK		(0x1 << 2)
#define BIT_REDGE		(0x1 << 1)
#define BIT_PIXEL_BIT		(0x1 << 0)

#define SHIFT_MCLKDIV		12

/* control reg 3 */
#define BIT_FRMCNT		(0xFFFF << 16)
#define BIT_FRMCNT_RST		(0x1 << 15)
#define BIT_DMA_REFLASH_RFF	(0x1 << 14)
#define BIT_DMA_REFLASH_SFF	(0x1 << 13)
#define BIT_DMA_REQ_EN_RFF	(0x1 << 12)
#define BIT_DMA_REQ_EN_SFF	(0x1 << 11)
#define BIT_STATFF_LEVEL	(0x7 << 8)
#define BIT_HRESP_ERR_EN	(0x1 << 7)
#define BIT_RXFF_LEVEL		(0x7 << 4)
#define BIT_TWO_8BIT_SENSOR	(0x1 << 3)
#define BIT_ZERO_PACK_EN	(0x1 << 2)
#define BIT_ECC_INT_EN		(0x1 << 1)
#define BIT_ECC_AUTO_EN		(0x1 << 0)

#define SHIFT_FRMCNT		16
#define SHIFT_RXFIFO_LEVEL	4

/* csi status reg */
#define BIT_ADDR_CH_ERR_INT (0x1 << 28)
#define BIT_FIELD0_INT      (0x1 << 27)
#define BIT_FIELD1_INT      (0x1 << 26)
#define BIT_SFF_OR_INT		(0x1 << 25)
#define BIT_RFF_OR_INT		(0x1 << 24)
#define BIT_DMA_TSF_DONE_SFF	(0x1 << 22)
#define BIT_STATFF_INT		(0x1 << 21)
#define BIT_DMA_TSF_DONE_FB2	(0x1 << 20)
#define BIT_DMA_TSF_DONE_FB1	(0x1 << 19)
#define BIT_RXFF_INT		(0x1 << 18)
#define BIT_EOF_INT		(0x1 << 17)
#define BIT_SOF_INT		(0x1 << 16)
#define BIT_F2_INT		(0x1 << 15)
#define BIT_F1_INT		(0x1 << 14)
#define BIT_COF_INT		(0x1 << 13)
#define BIT_HRESP_ERR_INT	(0x1 << 7)
#define BIT_ECC_INT		(0x1 << 1)
#define BIT_DRDY		(0x1 << 0)

/* csi control reg 18 */
#define BIT_CSI_ENABLE			(0x1 << 31)
#define BIT_MIPI_DATA_FORMAT_RAW8		(0x2a << 25)
#define BIT_MIPI_DATA_FORMAT_RAW10		(0x2b << 25)
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#define BIT_MIPI_DATA_FORMAT_RAW12		(0x2c << 25)
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#define BIT_MIPI_DATA_FORMAT_YUV422_8B	(0x1e << 25)
#define BIT_MIPI_DATA_FORMAT_MASK	(0x3F << 25)
#define BIT_MIPI_DATA_FORMAT_OFFSET	25
#define BIT_DATA_FROM_MIPI		(0x1 << 22)
#define BIT_MIPI_YU_SWAP		(0x1 << 21)
#define BIT_MIPI_DOUBLE_CMPNT	(0x1 << 20)
#define BIT_BASEADDR_CHG_ERR_EN	(0x1 << 9)
#define BIT_BASEADDR_SWITCH_SEL	(0x1 << 5)
#define BIT_BASEADDR_SWITCH_EN	(0x1 << 4)
#define BIT_PARALLEL24_EN		(0x1 << 3)
#define BIT_DEINTERLACE_EN		(0x1 << 2)
#define BIT_TVDECODER_IN_EN		(0x1 << 1)
#define BIT_NTSC_EN				(0x1 << 0)

#define CSI_MCLK_VF		1
#define CSI_MCLK_ENC		2
#define CSI_MCLK_RAW		4
#define CSI_MCLK_I2C		8

#define CSI_CSICR1		0x0
#define CSI_CSICR2		0x4
#define CSI_CSICR3		0x8
#define CSI_STATFIFO		0xC
#define CSI_CSIRXFIFO		0x10
#define CSI_CSIRXCNT		0x14
#define CSI_CSISR		0x18

#define CSI_CSIDBG		0x1C
#define CSI_CSIDMASA_STATFIFO	0x20
#define CSI_CSIDMATS_STATFIFO	0x24
#define CSI_CSIDMASA_FB1	0x28
#define CSI_CSIDMASA_FB2	0x2C
#define CSI_CSIFBUF_PARA	0x30
#define CSI_CSIIMAG_PARA	0x34

#define CSI_CSICR18		0x48
#define CSI_CSICR19		0x4c

#define NUM_FORMATS ARRAY_SIZE(formats)
#define MX6SX_MAX_SENSORS    1

struct csi_signal_cfg_t {
	unsigned data_width:3;
	unsigned clk_mode:2;
	unsigned ext_vsync:1;
	unsigned Vsync_pol:1;
	unsigned Hsync_pol:1;
	unsigned pixclk_pol:1;
	unsigned data_pol:1;
	unsigned sens_clksrc:1;
};

struct csi_config_t {
	/* control reg 1 */
	unsigned int swap16_en:1;
	unsigned int ext_vsync:1;
	unsigned int eof_int_en:1;
	unsigned int prp_if_en:1;
	unsigned int ccir_mode:1;
	unsigned int cof_int_en:1;
	unsigned int sf_or_inten:1;
	unsigned int rf_or_inten:1;
	unsigned int sff_dma_done_inten:1;
	unsigned int statff_inten:1;
	unsigned int fb2_dma_done_inten:1;
	unsigned int fb1_dma_done_inten:1;
	unsigned int rxff_inten:1;
	unsigned int sof_pol:1;
	unsigned int sof_inten:1;
	unsigned int mclkdiv:4;
	unsigned int hsync_pol:1;
	unsigned int ccir_en:1;
	unsigned int mclken:1;
	unsigned int fcc:1;
	unsigned int pack_dir:1;
	unsigned int gclk_mode:1;
	unsigned int inv_data:1;
	unsigned int inv_pclk:1;
	unsigned int redge:1;
	unsigned int pixel_bit:1;

	/* control reg 3 */
	unsigned int frmcnt:16;
	unsigned int frame_reset:1;
	unsigned int dma_reflash_rff:1;
	unsigned int dma_reflash_sff:1;
	unsigned int dma_req_en_rff:1;
	unsigned int dma_req_en_sff:1;
	unsigned int statff_level:3;
	unsigned int hresp_err_en:1;
	unsigned int rxff_level:3;
	unsigned int two_8bit_sensor:1;
	unsigned int zero_pack_en:1;
	unsigned int ecc_int_en:1;
	unsigned int ecc_auto_en:1;
	/* fifo counter */
	unsigned int rxcnt;
};

/*
 * Basic structures
 */
struct mx6s_fmt {
	char  name[32];
	u32   fourcc;		/* v4l2 format id */
	u32   pixelformat;
	u32   mbus_code;
	int   bpp;
};

static struct mx6s_fmt formats[] = {
	{
		.name		= "UYVY-16",
		.fourcc		= V4L2_PIX_FMT_UYVY,
		.pixelformat	= V4L2_PIX_FMT_UYVY,
		.mbus_code	= MEDIA_BUS_FMT_UYVY8_2X8,
		.bpp		= 2,
	}, {
		.name		= "YUYV-16",
		.fourcc		= V4L2_PIX_FMT_YUYV,
		.pixelformat	= V4L2_PIX_FMT_YUYV,
		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
		.bpp		= 2,
	}, {
		.name		= "YUV32 (X-Y-U-V)",
		.fourcc		= V4L2_PIX_FMT_YUV32,
		.pixelformat	= V4L2_PIX_FMT_YUV32,
		.mbus_code	= MEDIA_BUS_FMT_AYUV8_1X32,
		.bpp		= 4,
	}, {
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		.name		= "SBGGR8",
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		.fourcc		= V4L2_PIX_FMT_SBGGR8,
		.pixelformat	= V4L2_PIX_FMT_SBGGR8,
		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
		.bpp		= 1,
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	}, {
		.name		= "SBGGR10",
		.fourcc		= V4L2_PIX_FMT_SBGGR10,
		.pixelformat	= V4L2_PIX_FMT_SBGGR10,
		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
		.bpp		= 2,
	}, {
		.name		= "SBGGR12",
		.fourcc		= V4L2_PIX_FMT_SBGGR12,
		.pixelformat	= V4L2_PIX_FMT_SBGGR12,
		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
		.bpp		= 2,
	}, {
		.name		= "SGRBG8",
		.fourcc		= V4L2_PIX_FMT_SGRBG8,
		.pixelformat	= V4L2_PIX_FMT_SGRBG8,
		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
		.bpp		= 1,
	}, {
		.name		= "SGRBG10",
		.fourcc		= V4L2_PIX_FMT_SGRBG10,
		.pixelformat	= V4L2_PIX_FMT_SGRBG10,
		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
		.bpp		= 2,
	}, {
		.name		= "SGRBG12",
		.fourcc		= V4L2_PIX_FMT_SGRBG12,
		.pixelformat	= V4L2_PIX_FMT_SGRBG12,
		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
		.bpp		= 2,
	}, {
		.name		= "SGBRG8",
		.fourcc		= V4L2_PIX_FMT_SGBRG8,
		.pixelformat	= V4L2_PIX_FMT_SGBRG8,
		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
		.bpp		= 1,
	}, {
		.name		= "SGBRG10",
		.fourcc		= V4L2_PIX_FMT_SGBRG10,
		.pixelformat	= V4L2_PIX_FMT_SGBRG10,
		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
		.bpp		= 2,
	}, {
		.name		= "SGBRG12",
		.fourcc		= V4L2_PIX_FMT_SGBRG12,
		.pixelformat	= V4L2_PIX_FMT_SGBRG12,
		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
		.bpp		= 2,
	}, {
		.name		= "SRGGB8",
		.fourcc		= V4L2_PIX_FMT_SRGGB8,
		.pixelformat	= V4L2_PIX_FMT_SRGGB8,
		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
		.bpp		= 1,
	}, {
		.name		= "SRGGB10",
		.fourcc		= V4L2_PIX_FMT_SRGGB10,
		.pixelformat	= V4L2_PIX_FMT_SRGGB10,
		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
		.bpp		= 2,
	}, {
		.name		= "SRGGB12",
		.fourcc		= V4L2_PIX_FMT_SRGGB12,
		.pixelformat	= V4L2_PIX_FMT_SRGGB12,
		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
		.bpp		= 2,
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	}, {
		.name		= "Grey8 (Y8)",
		.fourcc		= V4L2_PIX_FMT_GREY,
		.pixelformat	= V4L2_PIX_FMT_GREY,
		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
		.bpp		= 1,
	}, {
		.name		= "Grey10 (Y10)",
		.fourcc		= V4L2_PIX_FMT_Y10,
		.pixelformat	= V4L2_PIX_FMT_Y10,
		.mbus_code	= MEDIA_BUS_FMT_Y10_1X10,
		.bpp		= 2,
	}, {
		.name		= "Grey12 (Y12)",
		.fourcc		= V4L2_PIX_FMT_Y12,
		.pixelformat	= V4L2_PIX_FMT_Y12,
		.mbus_code	= MEDIA_BUS_FMT_Y12_1X12,
		.bpp		= 2,
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	}
};

struct mx6s_buf_internal {
	struct list_head	queue;
	int					bufnum;
	bool				discard;
};

/* buffer for one video frame */
struct mx6s_buffer {
	/* common v4l buffer stuff -- must be first */
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	struct vb2_v4l2_buffer			vb;
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	struct mx6s_buf_internal	internal;
};

struct mx6s_csi_mux {
	struct regmap *gpr;
	u8 req_gpr;
	u8 req_bit;
};

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struct mx6s_csi_soc {
	bool rx_fifo_rst;
	int baseaddr_switch;
};

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struct mx6s_csi_dev {
	struct device		*dev;
	struct video_device *vdev;
	struct v4l2_subdev	*sd;
	struct v4l2_device	v4l2_dev;

	struct vb2_queue			vb2_vidq;
	struct v4l2_ctrl_handler	ctrl_handler;

	struct mutex		lock;
	spinlock_t			slock;

	/* clock */
	struct clk	*clk_disp_axi;
	struct clk	*clk_disp_dcic;
	struct clk	*clk_csi_mclk;

	void __iomem *regbase;
	int irq;

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	u32      nextfb;
	u32      skipframe;
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	u32	 type;
	u32 bytesperline;
	v4l2_std_id std;
	struct mx6s_fmt		*fmt;
	struct v4l2_pix_format pix;
	u32 mbus_code;

	unsigned int frame_count;

	struct list_head	capture;
	struct list_head	active_bufs;
	struct list_head	discard;

	void						*discard_buffer;
	dma_addr_t					discard_buffer_dma;
	size_t						discard_size;
	struct mx6s_buf_internal	buf_discard[2];

	struct v4l2_async_subdev	asd;
	struct v4l2_async_notifier	subdev_notifier;
	struct v4l2_async_subdev	*async_subdevs[2];

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	bool csi_mipi_mode;
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	bool csi_two_8bit_sensor_mode;
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	const struct mx6s_csi_soc *soc;
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	struct mx6s_csi_mux csi_mux;
};

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static const struct of_device_id mx6s_csi_dt_ids[];

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static inline int csi_read(struct mx6s_csi_dev *csi, unsigned int offset)
{
	return __raw_readl(csi->regbase + offset);
}
static inline void csi_write(struct mx6s_csi_dev *csi, unsigned int value,
			     unsigned int offset)
{
	__raw_writel(value, csi->regbase + offset);
}

static inline struct mx6s_csi_dev
				*notifier_to_mx6s_dev(struct v4l2_async_notifier *n)
{
	return container_of(n, struct mx6s_csi_dev, subdev_notifier);
}

struct mx6s_fmt *format_by_fourcc(int fourcc)
{
	int i;

	for (i = 0; i < NUM_FORMATS; i++) {
		if (formats[i].pixelformat == fourcc)
			return formats + i;
	}

	pr_err("unknown pixelformat:'%4.4s'\n", (char *)&fourcc);
	return NULL;
}

struct mx6s_fmt *format_by_mbus(u32 code)
{
	int i;

	for (i = 0; i < NUM_FORMATS; i++) {
		if (formats[i].mbus_code == code)
			return formats + i;
	}

	pr_err("unknown mbus:0x%x\n", code);
	return NULL;
}

static struct mx6s_buffer *mx6s_ibuf_to_buf(struct mx6s_buf_internal *int_buf)
{
	return container_of(int_buf, struct mx6s_buffer, internal);
}

void csi_clk_enable(struct mx6s_csi_dev *csi_dev)
{
	clk_prepare_enable(csi_dev->clk_disp_axi);
	clk_prepare_enable(csi_dev->clk_disp_dcic);
	clk_prepare_enable(csi_dev->clk_csi_mclk);
}

void csi_clk_disable(struct mx6s_csi_dev *csi_dev)
{
	clk_disable_unprepare(csi_dev->clk_csi_mclk);
	clk_disable_unprepare(csi_dev->clk_disp_dcic);
	clk_disable_unprepare(csi_dev->clk_disp_axi);
}

static void csihw_reset(struct mx6s_csi_dev *csi_dev)
{
	__raw_writel(__raw_readl(csi_dev->regbase + CSI_CSICR3)
			| BIT_FRMCNT_RST,
			csi_dev->regbase + CSI_CSICR3);

	__raw_writel(CSICR1_RESET_VAL, csi_dev->regbase + CSI_CSICR1);
	__raw_writel(CSICR2_RESET_VAL, csi_dev->regbase + CSI_CSICR2);
	__raw_writel(CSICR3_RESET_VAL, csi_dev->regbase + CSI_CSICR3);
}

static void csisw_reset(struct mx6s_csi_dev *csi_dev)
{
	int cr1, cr3, cr18, isr;

	/* Disable csi  */
	cr18 = csi_read(csi_dev, CSI_CSICR18);
	cr18 &= ~BIT_CSI_ENABLE;
	csi_write(csi_dev, cr18, CSI_CSICR18);

	/* Clear RX FIFO */
	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 & ~BIT_FCC, CSI_CSICR1);
	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);

	/* DMA reflash */
	cr3 = csi_read(csi_dev, CSI_CSICR3);
	cr3 |= BIT_DMA_REFLASH_RFF | BIT_FRMCNT_RST;
	csi_write(csi_dev, cr3, CSI_CSICR3);

	msleep(2);

	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 | BIT_FCC, CSI_CSICR1);

	isr = csi_read(csi_dev, CSI_CSISR);
	csi_write(csi_dev, isr, CSI_CSISR);

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	cr18 |= csi_dev->soc->baseaddr_switch;

	/* Enable csi  */
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	cr18 |= BIT_CSI_ENABLE;
	csi_write(csi_dev, cr18, CSI_CSICR18);
}

/*!
 * csi_init_interface
 *    Init csi interface
 */
static void csi_init_interface(struct mx6s_csi_dev *csi_dev)
{
	unsigned int val = 0;
	unsigned int imag_para;

	val |= BIT_SOF_POL;
	val |= BIT_REDGE;
	val |= BIT_GCLK_MODE;
	val |= BIT_HSYNC_POL;
	val |= BIT_FCC;
	val |= 1 << SHIFT_MCLKDIV;
	val |= BIT_MCLKEN;
	__raw_writel(val, csi_dev->regbase + CSI_CSICR1);

	imag_para = (640 << 16) | 960;
	__raw_writel(imag_para, csi_dev->regbase + CSI_CSIIMAG_PARA);

	val = BIT_DMA_REFLASH_RFF;
	__raw_writel(val, csi_dev->regbase + CSI_CSICR3);
}

static void csi_enable_int(struct mx6s_csi_dev *csi_dev, int arg)
{
	unsigned long cr1 = __raw_readl(csi_dev->regbase + CSI_CSICR1);

	cr1 |= BIT_SOF_INTEN;
	cr1 |= BIT_RFF_OR_INT;
	if (arg == 1) {
		/* still capture needs DMA intterrupt */
		cr1 |= BIT_FB1_DMA_DONE_INTEN;
		cr1 |= BIT_FB2_DMA_DONE_INTEN;
	}
	__raw_writel(cr1, csi_dev->regbase + CSI_CSICR1);
}

static void csi_disable_int(struct mx6s_csi_dev *csi_dev)
{
	unsigned long cr1 = __raw_readl(csi_dev->regbase + CSI_CSICR1);

	cr1 &= ~BIT_SOF_INTEN;
	cr1 &= ~BIT_RFF_OR_INT;
	cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
	cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
	__raw_writel(cr1, csi_dev->regbase + CSI_CSICR1);
}

static void csi_enable(struct mx6s_csi_dev *csi_dev, int arg)
{
	unsigned long cr = __raw_readl(csi_dev->regbase + CSI_CSICR18);

	if (arg == 1)
		cr |= BIT_CSI_ENABLE;
	else
		cr &= ~BIT_CSI_ENABLE;
	__raw_writel(cr, csi_dev->regbase + CSI_CSICR18);
}

static void csi_buf_stride_set(struct mx6s_csi_dev *csi_dev, u32 stride)
{
	__raw_writel(stride, csi_dev->regbase + CSI_CSIFBUF_PARA);
}

static void csi_deinterlace_enable(struct mx6s_csi_dev *csi_dev, bool enable)
{
	unsigned long cr18 = __raw_readl(csi_dev->regbase + CSI_CSICR18);

	if (enable == true)
		cr18 |= BIT_DEINTERLACE_EN;
	else
		cr18 &= ~BIT_DEINTERLACE_EN;

	__raw_writel(cr18, csi_dev->regbase + CSI_CSICR18);
}

static void csi_deinterlace_mode(struct mx6s_csi_dev *csi_dev, int mode)
{
	unsigned long cr18 = __raw_readl(csi_dev->regbase + CSI_CSICR18);

	if (mode == V4L2_STD_NTSC)
		cr18 |= BIT_NTSC_EN;
	else
		cr18 &= ~BIT_NTSC_EN;

	__raw_writel(cr18, csi_dev->regbase + CSI_CSICR18);
}

static void csi_tvdec_enable(struct mx6s_csi_dev *csi_dev, bool enable)
{
	unsigned long cr18 = __raw_readl(csi_dev->regbase + CSI_CSICR18);
	unsigned long cr1 = __raw_readl(csi_dev->regbase + CSI_CSICR1);

	if (enable == true) {
		cr18 |= (BIT_TVDECODER_IN_EN |
				BIT_BASEADDR_SWITCH_EN |
				BIT_BASEADDR_SWITCH_SEL |
				BIT_BASEADDR_CHG_ERR_EN);
		cr1 |= BIT_CCIR_MODE;
		cr1 &= ~(BIT_SOF_POL | BIT_REDGE);
	} else {
		cr18 &= ~(BIT_TVDECODER_IN_EN |
				BIT_BASEADDR_SWITCH_EN |
				BIT_BASEADDR_SWITCH_SEL |
				BIT_BASEADDR_CHG_ERR_EN);
		cr1 &= ~BIT_CCIR_MODE;
		cr1 |= BIT_SOF_POL | BIT_REDGE;
	}

	__raw_writel(cr18, csi_dev->regbase + CSI_CSICR18);
	__raw_writel(cr1, csi_dev->regbase + CSI_CSICR1);
}

static void csi_dmareq_rff_enable(struct mx6s_csi_dev *csi_dev)
{
	unsigned long cr3 = __raw_readl(csi_dev->regbase + CSI_CSICR3);
	unsigned long cr2 = __raw_readl(csi_dev->regbase + CSI_CSICR2);

	/* Burst Type of DMA Transfer from RxFIFO. INCR16 */
	cr2 |= 0xC0000000;

	cr3 |= BIT_DMA_REQ_EN_RFF;
	cr3 |= BIT_HRESP_ERR_EN;
	cr3 &= ~BIT_RXFF_LEVEL;
	cr3 |= 0x2 << 4;
674 675
	if (csi_dev->csi_two_8bit_sensor_mode)
		cr3 |= BIT_TWO_8BIT_SENSOR;
676 677 678 679 680 681 682 683 684 685 686 687 688 689

	__raw_writel(cr3, csi_dev->regbase + CSI_CSICR3);
	__raw_writel(cr2, csi_dev->regbase + CSI_CSICR2);
}

static void csi_dmareq_rff_disable(struct mx6s_csi_dev *csi_dev)
{
	unsigned long cr3 = __raw_readl(csi_dev->regbase + CSI_CSICR3);

	cr3 &= ~BIT_DMA_REQ_EN_RFF;
	cr3 &= ~BIT_HRESP_ERR_EN;
	__raw_writel(cr3, csi_dev->regbase + CSI_CSICR3);
}

690
static void csi_set_imagpara(struct mx6s_csi_dev *csi,
691 692 693 694 695 696 697 698 699 700 701 702
					int width, int height)
{
	int imag_para = 0;
	unsigned long cr3 = __raw_readl(csi->regbase + CSI_CSICR3);

	imag_para = (width << 16) | height;
	__raw_writel(imag_para, csi->regbase + CSI_CSIIMAG_PARA);

	/* reflash the embeded DMA controller */
	__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, csi->regbase + CSI_CSICR3);
}

703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731
static void csi_error_recovery(struct mx6s_csi_dev *csi_dev)
{
	u32 cr1, cr3, cr18;
	/* software reset */

	/* Disable csi  */
	cr18 = csi_read(csi_dev, CSI_CSICR18);
	cr18 &= ~BIT_CSI_ENABLE;
	csi_write(csi_dev, cr18, CSI_CSICR18);

	/* Clear RX FIFO */
	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 & ~BIT_FCC, CSI_CSICR1);
	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);

	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 | BIT_FCC, CSI_CSICR1);

	/* DMA reflash */
	cr3 = csi_read(csi_dev, CSI_CSICR3);
	cr3 |= BIT_DMA_REFLASH_RFF;
	csi_write(csi_dev, cr3, CSI_CSICR3);

	/* Ensable csi  */
	cr18 |= BIT_CSI_ENABLE;
	csi_write(csi_dev, cr18, CSI_CSICR18);
}

732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791
/*
 *  Videobuf operations
 */
static int mx6s_videobuf_setup(struct vb2_queue *vq,
			unsigned int *count, unsigned int *num_planes,
			unsigned int sizes[], struct device *alloc_devs[])
{
	struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vq);

	dev_dbg(csi_dev->dev, "count=%d, size=%d\n", *count, sizes[0]);

	alloc_devs[0] = csi_dev->dev;

	sizes[0] = csi_dev->pix.sizeimage;

	pr_debug("size=%d\n", sizes[0]);
	if (0 == *count)
		*count = 32;
	if (!*num_planes &&
	    sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
		*count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];

	*num_planes = 1;

	return 0;
}

static int mx6s_videobuf_prepare(struct vb2_buffer *vb)
{
	struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vb->vb2_queue);
	int ret = 0;

	dev_dbg(csi_dev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
		vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));

#ifdef DEBUG
	/*
	 * This can be useful if you want to see if we actually fill
	 * the buffer with something
	 */
	if (vb2_plane_vaddr(vb, 0))
		memset((void *)vb2_plane_vaddr(vb, 0),
		       0xaa, vb2_get_plane_payload(vb, 0));
#endif

	vb2_set_plane_payload(vb, 0, csi_dev->pix.sizeimage);
	if (vb2_plane_vaddr(vb, 0) &&
	    vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
		ret = -EINVAL;
		goto out;
	}

	return 0;

out:
	return ret;
}

static void mx6s_videobuf_queue(struct vb2_buffer *vb)
{
792
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
793
	struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vb->vb2_queue);
794
	struct mx6s_buffer *buf = container_of(vbuf, struct mx6s_buffer, vb);
795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838
	unsigned long flags;

	dev_dbg(csi_dev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
		vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));

	spin_lock_irqsave(&csi_dev->slock, flags);

	list_add_tail(&buf->internal.queue, &csi_dev->capture);

	spin_unlock_irqrestore(&csi_dev->slock, flags);
}

static void mx6s_update_csi_buf(struct mx6s_csi_dev *csi_dev,
				 unsigned long phys, int bufnum)
{
	if (bufnum == 1)
		csi_write(csi_dev, phys, CSI_CSIDMASA_FB2);
	else
		csi_write(csi_dev, phys, CSI_CSIDMASA_FB1);
}

static void mx6s_csi_init(struct mx6s_csi_dev *csi_dev)
{
	csi_clk_enable(csi_dev);
	csihw_reset(csi_dev);
	csi_init_interface(csi_dev);
	csi_dmareq_rff_disable(csi_dev);
}

static void mx6s_csi_deinit(struct mx6s_csi_dev *csi_dev)
{
	csihw_reset(csi_dev);
	csi_init_interface(csi_dev);
	csi_dmareq_rff_disable(csi_dev);
	csi_clk_disable(csi_dev);
}

static int mx6s_csi_enable(struct mx6s_csi_dev *csi_dev)
{
	struct v4l2_pix_format *pix = &csi_dev->pix;
	unsigned long flags;
	unsigned long val;
	int timeout, timeout2;

839
	csi_dev->skipframe = 0;
840 841 842 843 844 845
	csisw_reset(csi_dev);

	if (pix->field == V4L2_FIELD_INTERLACED)
		csi_tvdec_enable(csi_dev, true);

	/* For mipi csi input only */
846
	if (csi_dev->csi_mipi_mode == true) {
847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917
		csi_dmareq_rff_enable(csi_dev);
		csi_enable_int(csi_dev, 1);
		csi_enable(csi_dev, 1);
		return 0;
	}

	local_irq_save(flags);
	for (timeout = 10000000; timeout > 0; timeout--) {
		if (csi_read(csi_dev, CSI_CSISR) & BIT_SOF_INT) {
			val = csi_read(csi_dev, CSI_CSICR3);
			csi_write(csi_dev, val | BIT_DMA_REFLASH_RFF,
					CSI_CSICR3);
			/* Wait DMA reflash done */
			for (timeout2 = 1000000; timeout2 > 0; timeout2--) {
				if (csi_read(csi_dev, CSI_CSICR3) &
					BIT_DMA_REFLASH_RFF)
					cpu_relax();
				else
					break;
			}
			if (timeout2 <= 0) {
				pr_err("timeout when wait for reflash done.\n");
				local_irq_restore(flags);
				return -ETIME;
			}
			/* For imx6sl csi, DMA FIFO will auto start when sensor ready to work,
			 * so DMA should enable right after FIFO reset, otherwise dma will lost data
			 * and image will split.
			 */
			csi_dmareq_rff_enable(csi_dev);
			csi_enable_int(csi_dev, 1);
			csi_enable(csi_dev, 1);
			break;
		} else
			cpu_relax();
	}
	if (timeout <= 0) {
		pr_err("timeout when wait for SOF\n");
		local_irq_restore(flags);
		return -ETIME;
	}
	local_irq_restore(flags);

	return 0;
}

static void mx6s_csi_disable(struct mx6s_csi_dev *csi_dev)
{
	struct v4l2_pix_format *pix = &csi_dev->pix;

	csi_dmareq_rff_disable(csi_dev);
	csi_disable_int(csi_dev);

	/* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */
	csi_write(csi_dev, 0, CSI_CSIDMASA_FB1);
	csi_write(csi_dev, 0, CSI_CSIDMASA_FB2);

	csi_buf_stride_set(csi_dev, 0);

	if (pix->field == V4L2_FIELD_INTERLACED) {
		csi_deinterlace_enable(csi_dev, false);
		csi_tvdec_enable(csi_dev, false);
	}

	csi_enable(csi_dev, 0);
}

static int mx6s_configure_csi(struct mx6s_csi_dev *csi_dev)
{
	struct v4l2_pix_format *pix = &csi_dev->pix;
	u32 cr1, cr18;
918
	u32 width;
919 920 921 922 923 924 925 926 927 928 929

	if (pix->field == V4L2_FIELD_INTERLACED) {
		csi_deinterlace_enable(csi_dev, true);
		csi_buf_stride_set(csi_dev, csi_dev->pix.width);
		csi_deinterlace_mode(csi_dev, csi_dev->std);
	} else {
		csi_deinterlace_enable(csi_dev, false);
		csi_buf_stride_set(csi_dev, 0);
	}

	switch (csi_dev->fmt->pixelformat) {
930
	case V4L2_PIX_FMT_GREY:
931
	case V4L2_PIX_FMT_YUV32:
932
	case V4L2_PIX_FMT_SBGGR8:
933 934 935
	case V4L2_PIX_FMT_SGRBG8:
	case V4L2_PIX_FMT_SGBRG8:
	case V4L2_PIX_FMT_SRGGB8:
936
		width = pix->width;
937
		break;
938 939
	case V4L2_PIX_FMT_Y10:
	case V4L2_PIX_FMT_Y12:
940 941 942 943 944 945 946 947
	case V4L2_PIX_FMT_SBGGR10:
	case V4L2_PIX_FMT_SGRBG10:
	case V4L2_PIX_FMT_SGBRG10:
	case V4L2_PIX_FMT_SRGGB10:
	case V4L2_PIX_FMT_SBGGR12:
	case V4L2_PIX_FMT_SGRBG12:
	case V4L2_PIX_FMT_SGBRG12:
	case V4L2_PIX_FMT_SRGGB12:
948 949
	case V4L2_PIX_FMT_UYVY:
	case V4L2_PIX_FMT_YUYV:
950
		if (csi_dev->csi_mipi_mode == true)
951 952 953 954
			width = pix->width;
		else
			/* For parallel 8-bit sensor input */
			width = pix->width * 2;
955 956 957 958 959
		break;
	default:
		pr_debug("   case not supported\n");
		return -EINVAL;
	}
960
	csi_set_imagpara(csi_dev, width, pix->height);
961

962
	if (csi_dev->csi_mipi_mode == true) {
963 964
		cr1 = csi_read(csi_dev, CSI_CSICR1);
		cr1 &= ~BIT_GCLK_MODE;
965
		cr1 &= ~BIT_PIXEL_BIT;
966 967

		cr18 = csi_read(csi_dev, CSI_CSICR18);
968
		cr18 &= ~BIT_MIPI_DATA_FORMAT_MASK;
969 970 971 972 973 974 975 976
		cr18 |= BIT_DATA_FROM_MIPI;

		switch (csi_dev->fmt->pixelformat) {
		case V4L2_PIX_FMT_UYVY:
		case V4L2_PIX_FMT_YUYV:
			cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;
			break;
		case V4L2_PIX_FMT_SBGGR8:
977 978 979
		case V4L2_PIX_FMT_SGRBG8:
		case V4L2_PIX_FMT_SGBRG8:
		case V4L2_PIX_FMT_SRGGB8:
980
		case V4L2_PIX_FMT_GREY:
981 982
			cr18 |= BIT_MIPI_DATA_FORMAT_RAW8;
			break;
983 984 985 986
		case V4L2_PIX_FMT_SBGGR10:
		case V4L2_PIX_FMT_SGRBG10:
		case V4L2_PIX_FMT_SGBRG10:
		case V4L2_PIX_FMT_SRGGB10:
987 988
		case V4L2_PIX_FMT_Y10:
			cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
989
			cr1  |= BIT_PIXEL_BIT;
990
			break;
991 992 993 994
		case V4L2_PIX_FMT_SBGGR12:
		case V4L2_PIX_FMT_SGRBG12:
		case V4L2_PIX_FMT_SGBRG12:
		case V4L2_PIX_FMT_SRGGB12:
995 996
		case V4L2_PIX_FMT_Y12:
			cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
997
			cr1  |= BIT_PIXEL_BIT;
998
			break;
999 1000 1001 1002 1003
		default:
			pr_debug("   fmt not supported\n");
			return -EINVAL;
		}

1004
		csi_write(csi_dev, cr1, CSI_CSICR1);
1005 1006 1007 1008 1009
		csi_write(csi_dev, cr18, CSI_CSICR18);
	}
	return 0;
}

1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
static void mx6s_release_bufs(struct list_head *bufs,
			      enum vb2_buffer_state state)
{
	while (!list_empty(bufs)) {
		struct mx6s_buffer	*buf =
			list_first_entry(bufs, struct mx6s_buffer, internal.queue);

		list_del_init(&buf->internal.queue);
		vb2_buffer_done(&buf->vb.vb2_buf, state);
	}
}

1022 1023 1024
static int mx6s_start_streaming(struct vb2_queue *vq, unsigned int count)
{
	struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vq);
1025
	struct v4l2_subdev *sd = csi_dev->sd;
1026 1027 1028 1029
	struct vb2_buffer *vb;
	struct mx6s_buffer *buf;
	unsigned long phys;
	unsigned long flags;
1030
	int rc;
1031 1032 1033 1034

	if (count < 2)
		return -ENOBUFS;

1035 1036 1037 1038
	rc = v4l2_subdev_call(sd, video, s_stream, 1);
	if (rc < 0)
		return rc;

1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
	/*
	 * I didn't manage to properly enable/disable
	 * a per frame basis during running transfers,
	 * thus we allocate a buffer here and use it to
	 * discard frames when no buffer is available.
	 * Feel free to work on this ;)
	 */
	csi_dev->discard_size = csi_dev->pix.sizeimage;
	csi_dev->discard_buffer = dma_alloc_coherent(csi_dev->v4l2_dev.dev,
					PAGE_ALIGN(csi_dev->discard_size),
					&csi_dev->discard_buffer_dma,
					GFP_DMA | GFP_KERNEL);
1051 1052 1053 1054
	if (!csi_dev->discard_buffer) {
		rc = -ENOMEM;
		goto out;
	}
1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069

	spin_lock_irqsave(&csi_dev->slock, flags);

	csi_dev->buf_discard[0].discard = true;
	list_add_tail(&csi_dev->buf_discard[0].queue,
		      &csi_dev->discard);

	csi_dev->buf_discard[1].discard = true;
	list_add_tail(&csi_dev->buf_discard[1].queue,
		      &csi_dev->discard);

	/* csi buf 0 */
	buf = list_first_entry(&csi_dev->capture, struct mx6s_buffer,
			       internal.queue);
	buf->internal.bufnum = 0;
1070
	vb = &buf->vb.vb2_buf;
1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081
	vb->state = VB2_BUF_STATE_ACTIVE;

	phys = vb2_dma_contig_plane_dma_addr(vb, 0);

	mx6s_update_csi_buf(csi_dev, phys, buf->internal.bufnum);
	list_move_tail(csi_dev->capture.next, &csi_dev->active_bufs);

	/* csi buf 1 */
	buf = list_first_entry(&csi_dev->capture, struct mx6s_buffer,
			       internal.queue);
	buf->internal.bufnum = 1;
1082
	vb = &buf->vb.vb2_buf;
1083 1084 1085 1086 1087 1088
	vb->state = VB2_BUF_STATE_ACTIVE;

	phys = vb2_dma_contig_plane_dma_addr(vb, 0);
	mx6s_update_csi_buf(csi_dev, phys, buf->internal.bufnum);
	list_move_tail(csi_dev->capture.next, &csi_dev->active_bufs);

1089 1090
	csi_dev->nextfb = 0;

1091 1092
	spin_unlock_irqrestore(&csi_dev->slock, flags);

1093 1094 1095 1096
	rc = mx6s_csi_enable(csi_dev);
	if (rc < 0) {
		spin_lock_irqsave(&csi_dev->slock, flags);

1097 1098 1099 1100 1101 1102 1103
		dma_free_coherent(csi_dev->v4l2_dev.dev,
				  csi_dev->discard_size,
				  csi_dev->discard_buffer,
				  csi_dev->discard_buffer_dma);

		csi_dev->discard_buffer = NULL;

1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
		mx6s_release_bufs(&csi_dev->active_bufs, VB2_BUF_STATE_QUEUED);
		mx6s_release_bufs(&csi_dev->capture, VB2_BUF_STATE_QUEUED);

		spin_unlock_irqrestore(&csi_dev->slock, flags);

		goto out;
	}

	rc = 0;

out:
1115 1116 1117
	if (rc < 0)
		v4l2_subdev_call(sd, video, s_stream, 0);

1118
	return rc;
1119 1120 1121 1122 1123
}

static void mx6s_stop_streaming(struct vb2_queue *vq)
{
	struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vq);
1124
	struct v4l2_subdev *sd = csi_dev->sd;
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135
	unsigned long flags;
	struct mx6s_buffer *buf, *tmp;
	void *b;

	mx6s_csi_disable(csi_dev);

	spin_lock_irqsave(&csi_dev->slock, flags);

	list_for_each_entry_safe(buf, tmp,
				&csi_dev->active_bufs, internal.queue) {
		list_del_init(&buf->internal.queue);
1136 1137
		if (buf->vb.vb2_buf.state == VB2_BUF_STATE_ACTIVE)
			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1138 1139 1140 1141 1142
	}

	list_for_each_entry_safe(buf, tmp,
				&csi_dev->capture, internal.queue) {
		list_del_init(&buf->internal.queue);
1143 1144
		if (buf->vb.vb2_buf.state == VB2_BUF_STATE_ACTIVE)
			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158
	}

	INIT_LIST_HEAD(&csi_dev->capture);
	INIT_LIST_HEAD(&csi_dev->active_bufs);
	INIT_LIST_HEAD(&csi_dev->discard);

	b = csi_dev->discard_buffer;
	csi_dev->discard_buffer = NULL;

	spin_unlock_irqrestore(&csi_dev->slock, flags);

	dma_free_coherent(csi_dev->v4l2_dev.dev,
				csi_dev->discard_size, b,
				csi_dev->discard_buffer_dma);
1159 1160

	v4l2_subdev_call(sd, video, s_stream, 0);
1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
}

static struct vb2_ops mx6s_videobuf_ops = {
	.queue_setup     = mx6s_videobuf_setup,
	.buf_prepare     = mx6s_videobuf_prepare,
	.buf_queue       = mx6s_videobuf_queue,
	.wait_prepare    = vb2_ops_wait_prepare,
	.wait_finish     = vb2_ops_wait_finish,
	.start_streaming = mx6s_start_streaming,
	.stop_streaming	 = mx6s_stop_streaming,
};

static void mx6s_csi_frame_done(struct mx6s_csi_dev *csi_dev,
		int bufnum, bool err)
{
	struct mx6s_buf_internal *ibuf;
	struct mx6s_buffer *buf;
	struct vb2_buffer *vb;
	unsigned long phys;
1180 1181
	unsigned int phys_fb1;
	unsigned int phys_fb2;
1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194

	ibuf = list_first_entry(&csi_dev->active_bufs, struct mx6s_buf_internal,
			       queue);

	if (ibuf->discard) {
		/*
		 * Discard buffer must not be returned to user space.
		 * Just return it to the discard queue.
		 */
		list_move_tail(csi_dev->active_bufs.next, &csi_dev->discard);
	} else {
		buf = mx6s_ibuf_to_buf(ibuf);

1195
		vb = &buf->vb.vb2_buf;
1196 1197
		phys = vb2_dma_contig_plane_dma_addr(vb, 0);
		if (bufnum == 1) {
1198 1199
			phys_fb2 = csi_read(csi_dev, CSI_CSIDMASA_FB2);
			if (phys_fb2 != (u32)phys) {
1200
				dev_err(csi_dev->dev, "%lx != %x\n", phys,
1201
					phys_fb2);
1202 1203
			}
		} else {
1204 1205
			phys_fb1 = csi_read(csi_dev, CSI_CSIDMASA_FB1);
			if (phys_fb1 != (u32)phys) {
1206
				dev_err(csi_dev->dev, "%lx != %x\n", phys,
1207
					phys_fb1);
1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223
			}
		}
		dev_dbg(csi_dev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
				vb2_plane_vaddr(vb, 0),
				vb2_get_plane_payload(vb, 0));

		list_del_init(&buf->internal.queue);
		vb->timestamp =ktime_get_ns();
		to_vb2_v4l2_buffer(vb)->sequence = csi_dev->frame_count;
		if (err)
			vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
		else
			vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
	}

	csi_dev->frame_count++;
1224
	csi_dev->nextfb = (bufnum == 0 ? 1: 0);
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252

	/* Config discard buffer to active_bufs */
	if (list_empty(&csi_dev->capture)) {
		if (list_empty(&csi_dev->discard)) {
			dev_warn(csi_dev->dev,
					"%s: trying to access empty discard list\n",
					__func__);
			return;
		}

		ibuf = list_first_entry(&csi_dev->discard,
					struct mx6s_buf_internal, queue);
		ibuf->bufnum = bufnum;

		list_move_tail(csi_dev->discard.next, &csi_dev->active_bufs);

		mx6s_update_csi_buf(csi_dev,
					csi_dev->discard_buffer_dma, bufnum);
		return;
	}

	buf = list_first_entry(&csi_dev->capture, struct mx6s_buffer,
			       internal.queue);

	buf->internal.bufnum = bufnum;

	list_move_tail(csi_dev->capture.next, &csi_dev->active_bufs);

1253
	vb = &buf->vb.vb2_buf;
1254 1255 1256 1257 1258 1259 1260 1261 1262 1263
	vb->state = VB2_BUF_STATE_ACTIVE;

	phys = vb2_dma_contig_plane_dma_addr(vb, 0);
	mx6s_update_csi_buf(csi_dev, phys, bufnum);
}

static irqreturn_t mx6s_csi_irq_handler(int irq, void *data)
{
	struct mx6s_csi_dev *csi_dev =  data;
	unsigned long status;
1264
	u32 cr3, cr18;
1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279

	spin_lock(&csi_dev->slock);

	status = csi_read(csi_dev, CSI_CSISR);
	csi_write(csi_dev, status, CSI_CSISR);

	if (list_empty(&csi_dev->active_bufs)) {
		dev_warn(csi_dev->dev,
				"%s: called while active list is empty\n",
				__func__);

		spin_unlock(&csi_dev->slock);
		return IRQ_HANDLED;
	}

1280
	if (status & BIT_RFF_OR_INT) {
1281
		dev_warn(csi_dev->dev, "%s Rx fifo overflow\n", __func__);
1282
		if (csi_dev->soc->rx_fifo_rst)
1283 1284 1285 1286
			csi_error_recovery(csi_dev);
	}

	if (status & BIT_HRESP_ERR_INT) {
1287 1288
		dev_warn(csi_dev->dev, "%s Hresponse error detected\n",
			__func__);
1289
		csi_error_recovery(csi_dev);
1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
	}

	if (status & BIT_ADDR_CH_ERR_INT) {
		/* Disable csi  */
		cr18 = csi_read(csi_dev, CSI_CSICR18);
		cr18 &= ~BIT_CSI_ENABLE;
		csi_write(csi_dev, cr18, CSI_CSICR18);

		/* DMA reflash */
		cr3 = csi_read(csi_dev, CSI_CSICR3);
		cr3 |= BIT_DMA_REFLASH_RFF;
		csi_write(csi_dev, cr3, CSI_CSICR3);

		/* Ensable csi  */
		cr18 |= BIT_CSI_ENABLE;
		csi_write(csi_dev, cr18, CSI_CSICR18);

1307
		csi_dev->skipframe = 1;
1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321
		pr_debug("base address switching Change Err.\n");
	}

	if ((status & BIT_DMA_TSF_DONE_FB1) &&
		(status & BIT_DMA_TSF_DONE_FB2)) {
		/* For both FB1 and FB2 interrupter bits set case,
		 * CSI DMA is work in one of FB1 and FB2 buffer,
		 * but software can not know the state.
		 * Skip it to avoid base address updated
		 * when csi work in field0 and field1 will write to
		 * new base address.
		 * PDM TKT230775 */
		pr_debug("Skip two frames\n");
	} else if (status & BIT_DMA_TSF_DONE_FB1) {
1322 1323 1324 1325 1326 1327 1328 1329
		if (csi_dev->nextfb == 0) {
			if (csi_dev->skipframe > 0)
				csi_dev->skipframe--;
			else
				mx6s_csi_frame_done(csi_dev, 0, false);
		} else
			pr_warn("skip frame 0 \n");

1330
	} else if (status & BIT_DMA_TSF_DONE_FB2) {
1331 1332 1333 1334 1335 1336 1337
		if (csi_dev->nextfb == 1) {
			if (csi_dev->skipframe > 0)
				csi_dev->skipframe--;
			else
				mx6s_csi_frame_done(csi_dev, 1, false);
		} else
			pr_warn("skip frame 1 \n");
1338 1339 1340 1341 1342 1343 1344
	}

	spin_unlock(&csi_dev->slock);

	return IRQ_HANDLED;
}

1345
static int _mx6s_csi_open_init(struct mx6s_csi_dev *csi_dev)
1346 1347
{
	struct v4l2_subdev *sd = csi_dev->sd;
1348
	int ret;
1349 1350 1351 1352 1353

	pm_runtime_get_sync(csi_dev->dev);

	request_bus_freq(BUS_FREQ_HIGH);

1354 1355 1356
	ret = v4l2_subdev_call(sd, core, s_power, 1);
	if (ret < 0) {
		v4l2_err(sd, "failed to power on device: %d\n", ret);
1357
		pm_runtime_put(csi_dev->dev);
1358 1359
		goto out;
	}
1360

1361 1362
	mx6s_csi_init(csi_dev);

1363
	ret = 0;
1364

1365
out:
1366
	return ret;
1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
}

/*
 * File operations for the device
 */
static int mx6s_csi_open(struct file *file)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	int ret = 0;

	if (mutex_lock_interruptible(&csi_dev->lock))
		return -ERESTARTSYS;

	ret = v4l2_fh_open(file);
	if (ret < 0)
		goto out;

1384
	if (v4l2_fh_is_singular_file(file)) {
1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
		ret = _mx6s_csi_open_init(csi_dev);
		if (ret < 0) {
			v4l2_fh_release(file);
			goto out;
		}
	}

	ret = 0;

out:
1395
	mutex_unlock(&csi_dev->lock);
1396

1397 1398 1399 1400 1401 1402 1403
	return ret;
}

static int mx6s_csi_close(struct file *file)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;
1404
	int rc;
1405
	bool do_release;
1406 1407 1408

	mutex_lock(&csi_dev->lock);

1409
	do_release = v4l2_fh_is_singular_file(file);
1410

1411 1412
	rc = _vb2_fop_release(file, NULL);

1413 1414 1415 1416
	if (do_release) {
		mx6s_csi_deinit(csi_dev);
		v4l2_subdev_call(sd, core, s_power, 0);
		release_bus_freq(BUS_FREQ_HIGH);
1417
		pm_runtime_put(csi_dev->dev);
1418 1419 1420
	}

	mutex_unlock(&csi_dev->lock);
1421

1422
	return rc;
1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
}

static ssize_t mx6s_csi_read(struct file *file, char __user *buf,
			       size_t count, loff_t *ppos)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	int ret;

	dev_dbg(csi_dev->dev, "read called, buf %p\n", buf);

	mutex_lock(&csi_dev->lock);
	ret = vb2_read(&csi_dev->vb2_vidq, buf, count, ppos,
				file->f_flags & O_NONBLOCK);
	mutex_unlock(&csi_dev->lock);
	return ret;
}

static int mx6s_csi_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	int ret;

	if (mutex_lock_interruptible(&csi_dev->lock))
		return -ERESTARTSYS;
	ret = vb2_mmap(&csi_dev->vb2_vidq, vma);
	mutex_unlock(&csi_dev->lock);

	pr_debug("vma start=0x%08lx, size=%ld, ret=%d\n",
		(unsigned long)vma->vm_start,
		(unsigned long)vma->vm_end-(unsigned long)vma->vm_start,
		ret);

	return ret;
}

static struct v4l2_file_operations mx6s_csi_fops = {
	.owner		= THIS_MODULE,
	.open		= mx6s_csi_open,
	.release	= mx6s_csi_close,
	.read		= mx6s_csi_read,
	.poll		= vb2_fop_poll,
	.unlocked_ioctl	= video_ioctl2, /* V4L2 ioctl handler */
	.mmap		= mx6s_csi_mmap,
};

/*
 * Video node IOCTLs
 */
static int mx6s_vidioc_enum_input(struct file *file, void *priv,
				 struct v4l2_input *inp)
{
	if (inp->index != 0)
		return -EINVAL;

1477 1478 1479 1480 1481
	*inp = (struct v4l2_input) {
		.index	= inp->index,
		.type	= V4L2_INPUT_TYPE_CAMERA,
		.name	= "Camera",
	};
1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572

	return 0;
}

static int mx6s_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
	*i = 0;

	return 0;
}

static int mx6s_vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
	if (i > 0)
		return -EINVAL;

	return 0;
}

static int mx6s_vidioc_querystd(struct file *file, void *priv, v4l2_std_id *a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;

	return v4l2_subdev_call(sd, video, querystd, a);
}

static int mx6s_vidioc_s_std(struct file *file, void *priv, v4l2_std_id a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;

	return v4l2_subdev_call(sd, video, s_std, a);
}

static int mx6s_vidioc_g_std(struct file *file, void *priv, v4l2_std_id *a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;

	return v4l2_subdev_call(sd, video, g_std, a);
}

static int mx6s_vidioc_querybuf(struct file *file, void *priv,
			       struct v4l2_buffer *p)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	int ret;

	ret = vb2_querybuf(&csi_dev->vb2_vidq, p);

	if (!ret) {
		/* return physical address */
		struct vb2_buffer *vb = csi_dev->vb2_vidq.bufs[p->index];
		if (p->flags & V4L2_BUF_FLAG_MAPPED)
			p->m.offset = vb2_dma_contig_plane_dma_addr(vb, 0);
	}
	return ret;
}

static int mx6s_vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
				       struct v4l2_fmtdesc *f)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;
	struct v4l2_subdev_mbus_code_enum code = {
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
		.index = f->index,
	};
	struct mx6s_fmt *fmt;
	int ret;

	ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code);
	if (ret < 0) {
		/* no more formats */
		dev_dbg(csi_dev->dev, "No more fmt\n");
		return -EINVAL;
	}

	fmt = format_by_mbus(code.code);
	if (!fmt) {
		dev_err(csi_dev->dev, "mbus (0x%08x) invalid.\n", code.code);
		return -EINVAL;
	}

	strlcpy(f->description, fmt->name, sizeof(f->description));
	f->pixelformat = fmt->pixelformat;

	return 0;
}

1573 1574
static int _mx6s_vidioc_try_fmt_vid_cap(struct file *file, void *priv,
					struct v4l2_format *f, unsigned int which)
1575 1576 1577 1578 1579
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;
	struct v4l2_pix_format *pix = &f->fmt.pix;
	struct v4l2_subdev_format format = {
1580
		.which = which,
1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591
	};
	struct mx6s_fmt *fmt;
	int ret;

	fmt = format_by_fourcc(f->fmt.pix.pixelformat);
	if (!fmt) {
		dev_err(csi_dev->dev, "Fourcc format (0x%08x) invalid.",
			f->fmt.pix.pixelformat);
		return -EINVAL;
	}

1592 1593 1594 1595 1596 1597
	if (f->fmt.pix.width == 0 || f->fmt.pix.height == 0) {
		dev_err(csi_dev->dev, "width %d, height %d is too small.\n",
			f->fmt.pix.width, f->fmt.pix.height);
		return -EINVAL;
	}

1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610
	v4l2_fill_mbus_format(&format.format, pix, fmt->mbus_code);
	ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format);
	v4l2_fill_pix_format(pix, &format.format);

	if (pix->field != V4L2_FIELD_INTERLACED)
		pix->field = V4L2_FIELD_NONE;

	pix->sizeimage = fmt->bpp * pix->height * pix->width;
	pix->bytesperline = fmt->bpp * pix->width;

	return ret;
}

1611 1612 1613 1614 1615 1616
static int mx6s_vidioc_try_fmt_vid_cap(struct file *file, void *priv,
				       struct v4l2_format *f)
{
	return _mx6s_vidioc_try_fmt_vid_cap(file, priv, f, V4L2_SUBDEV_FORMAT_TRY);
}

1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
/*
 * The real work of figuring out a workable format.
 */

static int mx6s_vidioc_s_fmt_vid_cap(struct file *file, void *priv,
				    struct v4l2_format *f)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	int ret;

1627 1628
	ret = _mx6s_vidioc_try_fmt_vid_cap(file, csi_dev, f,
					   V4L2_SUBDEV_FORMAT_ACTIVE);
1629 1630 1631 1632 1633
	if (ret < 0)
		return ret;

	csi_dev->fmt           = format_by_fourcc(f->fmt.pix.pixelformat);
	csi_dev->mbus_code     = csi_dev->fmt->mbus_code;
1634
	csi_dev->pix           = f->fmt.pix;
1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670
	csi_dev->type          = f->type;
	dev_dbg(csi_dev->dev, "set to pixelformat '%4.6s'\n",
			(char *)&csi_dev->fmt->name);

	/* Config csi */
	mx6s_configure_csi(csi_dev);

	return 0;
}

static int mx6s_vidioc_g_fmt_vid_cap(struct file *file, void *priv,
				    struct v4l2_format *f)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);

	f->fmt.pix = csi_dev->pix;

	return 0;
}

static int mx6s_vidioc_querycap(struct file *file, void  *priv,
			       struct v4l2_capability *cap)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);

	/* cap->name is set by the friendly caller:-> */
	strlcpy(cap->driver, MX6S_CAM_DRV_NAME, sizeof(cap->driver));
	strlcpy(cap->card, MX6S_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
		 dev_name(csi_dev->dev));

	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
	return 0;
}

1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
static int mx6s_vidioc_expbuf(struct file *file, void *priv,
			     struct v4l2_exportbuffer *eb)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);

	if (eb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return vb2_expbuf(&csi_dev->vb2_vidq, eb);

	return -EINVAL;
}

1682 1683 1684 1685 1686 1687 1688 1689
static int mx6s_vidioc_streamon(struct file *file, void *priv,
			       enum v4l2_buf_type i)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);

	if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return -EINVAL;

1690
	return vb2_streamon(&csi_dev->vb2_vidq, i);
1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704
}

static int mx6s_vidioc_streamoff(struct file *file, void *priv,
				enum v4l2_buf_type i)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);

	if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return -EINVAL;

	/*
	 * This calls buf_release from host driver's videobuf_queue_ops for all
	 * remaining buffers. When the last buffer is freed, stop capture
	 */
1705
	return vb2_streamoff(&csi_dev->vb2_vidq, i);
1706 1707 1708 1709 1710 1711
}

static int mx6s_vidioc_cropcap(struct file *file, void *fh,
			      struct v4l2_cropcap *a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
1712 1713 1714 1715 1716 1717 1718 1719
	struct v4l2_subdev *sd = csi_dev->sd;
	struct v4l2_subdev_selection	sel = {
		.which	= V4L2_SUBDEV_FORMAT_ACTIVE,
		.pad	= 0,
		.target	= V4L2_SEL_TGT_CROP_BOUNDS,
		.flags	= 0,
	};
	int rc;
1720 1721 1722 1723

	if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return -EINVAL;

1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738
	rc = v4l2_subdev_call(sd, pad, get_selection, NULL, &sel);
	if (rc < 0)
		goto out;

	a->bounds = sel.r;
	a->defrect = sel.r;
	a->pixelaspect = (struct v4l2_fract) {
		.numerator = 1,
		.denominator = 1,
	};

	rc = 0;

out:
	return rc;
1739 1740 1741 1742 1743 1744
}

static int mx6s_vidioc_g_crop(struct file *file, void *priv,
			     struct v4l2_crop *a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
1745 1746 1747 1748 1749 1750 1751 1752
	struct v4l2_subdev *sd = csi_dev->sd;
	struct v4l2_subdev_selection	sel = {
		.which	= V4L2_SUBDEV_FORMAT_ACTIVE,
		.pad	= 0,
		.target	= V4L2_SEL_TGT_CROP,
		.flags	= 0,
	};
	int rc;
1753 1754 1755 1756

	if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return -EINVAL;

1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
	rc = v4l2_subdev_call(sd, pad, get_selection, NULL, &sel);
	if (rc < 0)
		goto out;

	a->c = sel.r;

	rc = 0;

out:
	return rc;
1767 1768 1769 1770 1771 1772
}

static int mx6s_vidioc_s_crop(struct file *file, void *priv,
			     const struct v4l2_crop *a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
1773 1774 1775 1776 1777 1778 1779 1780 1781
	struct v4l2_subdev *sd = csi_dev->sd;
	struct v4l2_subdev_selection	sel = {
		.which	= V4L2_SUBDEV_FORMAT_ACTIVE,
		.pad	= 0,
		.target	= V4L2_SEL_TGT_CROP,
		.flags	= 0,
		.r	= a->c,
	};
	int rc;
1782 1783 1784 1785

	if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return -EINVAL;

1786 1787 1788
	rc = v4l2_subdev_call(sd, pad, set_selection, NULL, &sel);
	if (rc < 0)
		goto out;
1789

1790 1791 1792
	rc = 0;

out:
1793 1794 1795
	return 0;
}

1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835
static int mx6s_vidioc_g_selection(struct file *file, void *fh,
				   struct v4l2_selection *s)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;
	struct v4l2_subdev_selection	sel = {
		.which	= V4L2_SUBDEV_FORMAT_ACTIVE,
		.pad	= 0,
		.target	= s->target,
		.flags	= s->flags,
	};
	int				rc;

	rc = v4l2_subdev_call(sd, pad, get_selection, NULL, &sel);
	if (rc < 0)
		goto out;

	s->r     = sel.r;
	s->flags = sel.flags;

out:
	return rc;
}

static int mx6s_vidioc_s_selection(struct file *file, void *fh,
				   struct v4l2_selection *s)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;
	struct v4l2_subdev_selection	sel = {
		.which	= V4L2_SUBDEV_FORMAT_ACTIVE,
		.pad	= 0,
		.target	= s->target,
		.flags	= s->flags,
		.r	= s->r,
	};

	return v4l2_subdev_call(sd, pad, set_selection, NULL, &sel);
}

1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866
static int mx6s_vidioc_g_parm(struct file *file, void *priv,
			     struct v4l2_streamparm *a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;

	return v4l2_subdev_call(sd, video, g_parm, a);
}

static int mx6s_vidioc_s_parm(struct file *file, void *priv,
				struct v4l2_streamparm *a)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;

	return v4l2_subdev_call(sd, video, s_parm, a);
}

static int mx6s_vidioc_enum_framesizes(struct file *file, void *priv,
					 struct v4l2_frmsizeenum *fsize)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;
	struct mx6s_fmt *fmt;
	struct v4l2_subdev_frame_size_enum fse = {
		.index = fsize->index,
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
	};
	int ret;

	fmt = format_by_fourcc(fsize->pixel_format);
1867
	if (!fmt || fmt->pixelformat != fsize->pixel_format)
1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882
		return -EINVAL;
	fse.code = fmt->mbus_code;

	ret = v4l2_subdev_call(sd, pad, enum_frame_size, NULL, &fse);
	if (ret)
		return ret;

	if (fse.min_width == fse.max_width &&
	    fse.min_height == fse.max_height) {
		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
		fsize->discrete.width = fse.min_width;
		fsize->discrete.height = fse.min_height;
		return 0;
	}

1883
	fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908
	fsize->stepwise.min_width = fse.min_width;
	fsize->stepwise.max_width = fse.max_width;
	fsize->stepwise.min_height = fse.min_height;
	fsize->stepwise.max_height = fse.max_height;
	fsize->stepwise.step_width = 1;
	fsize->stepwise.step_height = 1;

	return 0;
}

static int mx6s_vidioc_enum_frameintervals(struct file *file, void *priv,
		struct v4l2_frmivalenum *interval)
{
	struct mx6s_csi_dev *csi_dev = video_drvdata(file);
	struct v4l2_subdev *sd = csi_dev->sd;
	struct mx6s_fmt *fmt;
	struct v4l2_subdev_frame_interval_enum fie = {
		.index = interval->index,
		.width = interval->width,
		.height = interval->height,
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
	};
	int ret;

	fmt = format_by_fourcc(interval->pixel_format);
1909
	if (!fmt || fmt->pixelformat != interval->pixel_format)
1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929
		return -EINVAL;
	fie.code = fmt->mbus_code;

	ret = v4l2_subdev_call(sd, pad, enum_frame_interval, NULL, &fie);
	if (ret)
		return ret;
	interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
	interval->discrete = fie.interval;
	return 0;
}

static const struct v4l2_ioctl_ops mx6s_csi_ioctl_ops = {
	.vidioc_querycap          = mx6s_vidioc_querycap,
	.vidioc_enum_fmt_vid_cap  = mx6s_vidioc_enum_fmt_vid_cap,
	.vidioc_try_fmt_vid_cap   = mx6s_vidioc_try_fmt_vid_cap,
	.vidioc_g_fmt_vid_cap     = mx6s_vidioc_g_fmt_vid_cap,
	.vidioc_s_fmt_vid_cap     = mx6s_vidioc_s_fmt_vid_cap,
	.vidioc_cropcap       = mx6s_vidioc_cropcap,
	.vidioc_s_crop        = mx6s_vidioc_s_crop,
	.vidioc_g_crop        = mx6s_vidioc_g_crop,
1930 1931
	.vidioc_g_selection   = mx6s_vidioc_g_selection,
	.vidioc_s_selection   = mx6s_vidioc_s_selection,
1932 1933 1934 1935
	.vidioc_reqbufs       = vb2_ioctl_reqbufs,
	.vidioc_create_bufs   = vb2_ioctl_create_bufs,
	.vidioc_qbuf          = vb2_ioctl_qbuf,
	.vidioc_dqbuf         = vb2_ioctl_dqbuf,
1936 1937 1938 1939 1940 1941 1942
	.vidioc_querybuf      = mx6s_vidioc_querybuf,
	.vidioc_g_std         = mx6s_vidioc_g_std,
	.vidioc_s_std         = mx6s_vidioc_s_std,
	.vidioc_querystd      = mx6s_vidioc_querystd,
	.vidioc_enum_input    = mx6s_vidioc_enum_input,
	.vidioc_g_input       = mx6s_vidioc_g_input,
	.vidioc_s_input       = mx6s_vidioc_s_input,
1943
	.vidioc_expbuf        = mx6s_vidioc_expbuf,
1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970
	.vidioc_streamon      = mx6s_vidioc_streamon,
	.vidioc_streamoff     = mx6s_vidioc_streamoff,
	.vidioc_g_parm        = mx6s_vidioc_g_parm,
	.vidioc_s_parm        = mx6s_vidioc_s_parm,
	.vidioc_enum_framesizes = mx6s_vidioc_enum_framesizes,
	.vidioc_enum_frameintervals = mx6s_vidioc_enum_frameintervals,
};

static int subdev_notifier_bound(struct v4l2_async_notifier *notifier,
			    struct v4l2_subdev *subdev,
			    struct v4l2_async_subdev *asd)
{
	struct mx6s_csi_dev *csi_dev = notifier_to_mx6s_dev(notifier);

	/* Find platform data for this sensor subdev */
	if (csi_dev->asd.match.fwnode.fwnode == dev_fwnode(subdev->dev))
		csi_dev->sd = subdev;

	if (subdev == NULL)
		return -EINVAL;

	v4l2_info(&csi_dev->v4l2_dev, "Registered sensor subdevice: %s\n",
		  subdev->name);

	return 0;
}

1971
static int mx6s_csi_mode_sel(struct mx6s_csi_dev *csi_dev)
1972 1973 1974 1975 1976
{
	struct device_node *np = csi_dev->dev->of_node;
	struct device_node *node;
	phandle phandle;
	u32 out_val[3];
1977 1978 1979 1980 1981 1982 1983 1984
	int ret = 0;

	if (of_get_property(np, "fsl,mipi-mode", NULL))
		csi_dev->csi_mipi_mode = true;
	else {
		csi_dev->csi_mipi_mode = false;
		return ret;
	}
1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

	ret = of_property_read_u32_array(np, "csi-mux-mipi", out_val, 3);
	if (ret) {
		dev_dbg(csi_dev->dev, "no csi-mux-mipi property found\n");
	} else {
		phandle = *out_val;

		node = of_find_node_by_phandle(phandle);
		if (!node) {
			dev_dbg(csi_dev->dev, "not find gpr node by phandle\n");
			ret = PTR_ERR(node);
		}
		csi_dev->csi_mux.gpr = syscon_node_to_regmap(node);
		if (IS_ERR(csi_dev->csi_mux.gpr)) {
			dev_err(csi_dev->dev, "failed to get gpr regmap\n");
			ret = PTR_ERR(csi_dev->csi_mux.gpr);
		}
		of_node_put(node);
		if (ret < 0)
			return ret;

		csi_dev->csi_mux.req_gpr = out_val[1];
		csi_dev->csi_mux.req_bit = out_val[2];

		regmap_update_bits(csi_dev->csi_mux.gpr, csi_dev->csi_mux.req_gpr,
			1 << csi_dev->csi_mux.req_bit, 1 << csi_dev->csi_mux.req_bit);
	}
	return ret;
}

2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027
static int mx6s_csi_two_8bit_sensor_mode_sel(struct mx6s_csi_dev *csi_dev)
{
	struct device_node *np = csi_dev->dev->of_node;

	if (of_get_property(np, "fsl,two-8bit-sensor-mode", NULL))
		csi_dev->csi_two_8bit_sensor_mode = true;
	else {
		csi_dev->csi_two_8bit_sensor_mode = false;
	}

	return 0;
}

2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075
static int mx6sx_register_subdevs(struct mx6s_csi_dev *csi_dev)
{
	struct device_node *parent = csi_dev->dev->of_node;
	struct device_node *node, *port, *rem;
	int ret;

	/* Attach sensors linked to csi receivers */
	for_each_available_child_of_node(parent, node) {
		if (of_node_cmp(node->name, "port"))
			continue;

		/* The csi node can have only port subnode. */
		port = of_get_next_child(node, NULL);
		if (!port)
			continue;
		rem = of_graph_get_remote_port_parent(port);
		of_node_put(port);
		if (rem == NULL) {
			v4l2_info(&csi_dev->v4l2_dev,
						"Remote device at %s not found\n",
						port->full_name);
			return -1;
		}

		csi_dev->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
		csi_dev->asd.match.fwnode.fwnode = of_fwnode_handle(rem);
		csi_dev->async_subdevs[0] = &csi_dev->asd;

		of_node_put(rem);
		break;
	}

	csi_dev->subdev_notifier.subdevs = csi_dev->async_subdevs;
	csi_dev->subdev_notifier.num_subdevs = 1;
	csi_dev->subdev_notifier.bound = subdev_notifier_bound;

	ret = v4l2_async_notifier_register(&csi_dev->v4l2_dev,
					&csi_dev->subdev_notifier);
	if (ret)
		dev_err(csi_dev->dev,
					"Error register async notifier regoster\n");

	return ret;
}

static int mx6s_csi_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
2076
	const struct of_device_id *of_id;
2077 2078 2079
	struct mx6s_csi_dev *csi_dev;
	struct video_device *vdev;
	struct resource *res;
2080
	struct vb2_queue *q;
2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129
	int ret = 0;

	dev_dbg(dev, "initialising\n");

	/* Prepare our private structure */
	csi_dev = devm_kzalloc(dev, sizeof(struct mx6s_csi_dev), GFP_ATOMIC);
	if (!csi_dev) {
		dev_err(dev, "Can't allocate private structure\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	csi_dev->irq = platform_get_irq(pdev, 0);
	if (res == NULL || csi_dev->irq < 0) {
		dev_err(dev, "Missing platform resources data\n");
		return -ENODEV;
	}

	csi_dev->regbase = devm_ioremap_resource(dev, res);
	if (IS_ERR(csi_dev->regbase)) {
		dev_err(dev, "Failed platform resources map\n");
		return -ENODEV;
	}

	/* init video dma queues */
	INIT_LIST_HEAD(&csi_dev->capture);
	INIT_LIST_HEAD(&csi_dev->active_bufs);
	INIT_LIST_HEAD(&csi_dev->discard);

	csi_dev->clk_disp_axi = devm_clk_get(dev, "disp-axi");
	if (IS_ERR(csi_dev->clk_disp_axi)) {
		dev_err(dev, "Could not get csi axi clock\n");
		return -ENODEV;
	}

	csi_dev->clk_disp_dcic = de