Commit 2760b3a3 authored by Christian Hemp's avatar Christian Hemp

arm64: dts: Add support for PHYTEC i.MX8QM eval board

Add support for PHYTEC phyCORE-i.MX8 (PCM-064) with evaluation board
PCM-943.
    Support:
     * 4GB LPDDR4 RAM
     * eMMC
     * external SD
     * 2x 1Gbit Ethernet
     * UART
     * PCIe
     * SATA
     * LVDS Display
     * Touch
     * 2x CAN
     * FlexCAN
     * USB 3.0
Signed-off-by: default avatarChristian Hemp <c.hemp@phytec.de>
parent 79cb349f
......@@ -56,7 +56,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \
fsl-imx8qm-lpddr4-arm2-hsic.dtb \
fsl-imx8dm-lpddr4-arm2.dtb \
fsl-imx8qp-lpddr4-arm2.dtb \
fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb
fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb \
phytec-imx8qm-phycore-rdk.dtb
dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
fsl-imx8qxp-mek.dtb \
fsl-imx8qxp-mek-rpmsg.dtb \
......
This diff is collapsed.
/*
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Christian Hemp <c.hemp@phytec.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "phytec-imx8qm-phycore-som.dtsi"
#include "phytec-imx8qm-pcm-943.dtsi"
/*
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Christian Hemp <c.hemp@phytec.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8qm.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-i.MX8";
compatible = "phytec,imx8qm-pcm064", "fsl,imx8qm";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
user {
label = "heartbeat";
gpios = <&gpio1 22 0>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
};
&dpr1_channel1 {
status = "okay";
};
&dpr1_channel2 {
status = "okay";
};
&dpr1_channel3 {
status = "okay";
};
&dpr2_channel1 {
status = "okay";
};
&dpr2_channel2 {
status = "okay";
};
&dpr2_channel3 {
status = "okay";
};
&dpr3_channel1 {
status = "okay";
};
&dpr3_channel2 {
status = "okay";
};
&dpr3_channel3 {
status = "okay";
};
&dpr4_channel1 {
status = "okay";
};
&dpr4_channel2 {
status = "okay";
};
&dpr4_channel3 {
status = "okay";
};
&dpu1 {
status = "okay";
};
&dpu2 {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
fsl,mii-exclusive;
phy-reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
enet-phy-lane-no-swap;
};
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt35xu512aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,mt35xu512aba";
spi-max-frequency = <133000000>;
spi-nor,ddr-quad-read-dummy = <8>;
};
};
&gpu_3d0 {
status = "okay";
};
&gpu_3d1 {
status = "okay";
};
&imx8_gpu_ss {
status = "okay";
};
&pixel_combiner1 {
status = "okay";
};
&pixel_combiner2 {
status = "okay";
};
&prg1 {
status = "okay";
};
&prg2 {
status = "okay";
};
&prg3 {
status = "okay";
};
&prg4 {
status = "okay";
};
&prg5 {
status = "okay";
};
&prg6 {
status = "okay";
};
&prg7 {
status = "okay";
};
&prg8 {
status = "okay";
};
&prg9 {
status = "okay";
};
&prg10 {
status = "okay";
};
&prg11 {
status = "okay";
};
&prg12 {
status = "okay";
};
&prg13 {
status = "okay";
};
&prg14 {
status = "okay";
};
&prg15 {
status = "okay";
};
&prg16 {
status = "okay";
};
&prg17 {
status = "okay";
};
&prg18 {
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&vpu_decoder {
core_type = <2>;
status = "okay";
};
&vpu_encoder {
status = "okay";
};
&iomuxc {
imx8qm-phytec-phycore-som {
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000060
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000060
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000060
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000060
SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021
SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000021
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
};
};
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