...
 
Commits (7775)

Too many changes to show.

To preserve performance only 1000 of 1000+ files are displayed.

...@@ -1011,7 +1011,7 @@ ...@@ -1011,7 +1011,7 @@
earlyprintk=serial[,0x...[,baudrate]] earlyprintk=serial[,0x...[,baudrate]]
earlyprintk=ttySn[,baudrate] earlyprintk=ttySn[,baudrate]
earlyprintk=dbgp[debugController#] earlyprintk=dbgp[debugController#]
earlyprintk=pciserial,bus:device.function[,baudrate] earlyprintk=pciserial[,force],bus:device.function[,baudrate]
earlyprintk=xdbc[xhciController#] earlyprintk=xdbc[xhciController#]
earlyprintk is useful when the kernel crashes before earlyprintk is useful when the kernel crashes before
...@@ -1043,6 +1043,10 @@ ...@@ -1043,6 +1043,10 @@
The sclp output can only be used on s390. The sclp output can only be used on s390.
The optional "force" to "pciserial" enables use of a
PCI device even when its classcode is not of the
UART class.
edac_report= [HW,EDAC] Control how to report EDAC event edac_report= [HW,EDAC] Control how to report EDAC event
Format: {"on" | "off" | "force"} Format: {"on" | "off" | "force"}
on: enable EDAC to report H/W event. May be overridden on: enable EDAC to report H/W event. May be overridden
...@@ -1961,6 +1965,9 @@ ...@@ -1961,6 +1965,9 @@
off off
Disables hypervisor mitigations and doesn't Disables hypervisor mitigations and doesn't
emit any warnings. emit any warnings.
It also drops the swap size and available
RAM limit restriction on both hypervisor and
bare metal.
Default is 'flush'. Default is 'flush'.
...@@ -3990,9 +3997,13 @@ ...@@ -3990,9 +3997,13 @@
spectre_v2= [X86] Control mitigation of Spectre variant 2 spectre_v2= [X86] Control mitigation of Spectre variant 2
(indirect branch speculation) vulnerability. (indirect branch speculation) vulnerability.
The default operation protects the kernel from
user space attacks.
on - unconditionally enable on - unconditionally enable, implies
off - unconditionally disable spectre_v2_user=on
off - unconditionally disable, implies
spectre_v2_user=off
auto - kernel detects whether your CPU model is auto - kernel detects whether your CPU model is
vulnerable vulnerable
...@@ -4002,6 +4013,12 @@ ...@@ -4002,6 +4013,12 @@
CONFIG_RETPOLINE configuration option, and the CONFIG_RETPOLINE configuration option, and the
compiler with which the kernel was built. compiler with which the kernel was built.
Selecting 'on' will also enable the mitigation
against user space to user space task attacks.
Selecting 'off' will disable both the kernel and
the user space protections.
Specific mitigations can also be selected manually: Specific mitigations can also be selected manually:
retpoline - replace indirect branches retpoline - replace indirect branches
...@@ -4011,6 +4028,48 @@ ...@@ -4011,6 +4028,48 @@
Not specifying this option is equivalent to Not specifying this option is equivalent to
spectre_v2=auto. spectre_v2=auto.
spectre_v2_user=
[X86] Control mitigation of Spectre variant 2
(indirect branch speculation) vulnerability between
user space tasks
on - Unconditionally enable mitigations. Is
enforced by spectre_v2=on
off - Unconditionally disable mitigations. Is
enforced by spectre_v2=off
prctl - Indirect branch speculation is enabled,
but mitigation can be enabled via prctl
per thread. The mitigation control state
is inherited on fork.
prctl,ibpb
- Like "prctl" above, but only STIBP is
controlled per thread. IBPB is issued
always when switching between different user
space processes.
seccomp
- Same as "prctl" above, but all seccomp
threads will enable the mitigation unless
they explicitly opt out.
seccomp,ibpb
- Like "seccomp" above, but only STIBP is
controlled per thread. IBPB is issued
always when switching between different
user space processes.
auto - Kernel selects the mitigation depending on
the available CPU features and vulnerability.
Default mitigation:
If CONFIG_SECCOMP=y then "seccomp", otherwise "prctl"
Not specifying this option is equivalent to
spectre_v2_user=auto.
spec_store_bypass_disable= spec_store_bypass_disable=
[HW] Control Speculative Store Bypass (SSB) Disable mitigation [HW] Control Speculative Store Bypass (SSB) Disable mitigation
(Speculative Store Bypass vulnerability) (Speculative Store Bypass vulnerability)
......
...@@ -405,6 +405,9 @@ time with the option "l1tf=". The valid arguments for this option are: ...@@ -405,6 +405,9 @@ time with the option "l1tf=". The valid arguments for this option are:
off Disables hypervisor mitigations and doesn't emit any off Disables hypervisor mitigations and doesn't emit any
warnings. warnings.
It also drops the swap size and available RAM limit restrictions
on both hypervisor and bare metal.
============ ============================================================= ============ =============================================================
The default is 'flush'. For details about L1D flushing see :ref:`l1d_flush`. The default is 'flush'. For details about L1D flushing see :ref:`l1d_flush`.
...@@ -576,7 +579,8 @@ Default mitigations ...@@ -576,7 +579,8 @@ Default mitigations
The kernel default mitigations for vulnerable processors are: The kernel default mitigations for vulnerable processors are:
- PTE inversion to protect against malicious user space. This is done - PTE inversion to protect against malicious user space. This is done
unconditionally and cannot be controlled. unconditionally and cannot be controlled. The swap storage is limited
to ~16TB.
- L1D conditional flushing on VMENTER when EPT is enabled for - L1D conditional flushing on VMENTER when EPT is enabled for
a guest. a guest.
......
...@@ -587,6 +587,102 @@ This governor exposes the following tunables: ...@@ -587,6 +587,102 @@ This governor exposes the following tunables:
It effectively causes the frequency to go down ``sampling_down_factor`` It effectively causes the frequency to go down ``sampling_down_factor``
times slower than it ramps up. times slower than it ramps up.
``interactive``
---------------
The CPUfreq governor "interactive" is designed for latency-sensitive,
interactive workloads. This governor sets the CPU speed depending on
usage, similar to "ondemand" and "conservative" governors, but with a
different set of configurable behaviors.
The tunable values for this governor are:
``above_hispeed_delay``
When speed is at or above hispeed_freq, wait for
this long before raising speed in response to continued high load.
The format is a single delay value, optionally followed by pairs of
CPU speeds and the delay to use at or above those speeds. Colons can
be used between the speeds and associated delays for readability. For
example:
80000 1300000:200000 1500000:40000
uses delay 80000 uS until CPU speed 1.3 GHz, at which speed delay
200000 uS is used until speed 1.5 GHz, at which speed (and above)
delay 40000 uS is used. If speeds are specified these must appear in
ascending order. Default is 20000 uS.
``boost``
If non-zero, immediately boost speed of all CPUs to at least
hispeed_freq until zero is written to this attribute. If zero, allow
CPU speeds to drop below hispeed_freq according to load as usual.
Default is zero.
``boostpulse``
On each write, immediately boost speed of all CPUs to
hispeed_freq for at least the period of time specified by
boostpulse_duration, after which speeds are allowed to drop below
hispeed_freq according to load as usual. Its a write-only file.
``boostpulse_duration``
Length of time to hold CPU speed at hispeed_freq
on a write to boostpulse, before allowing speed to drop according to
load as usual. Default is 80000 uS.
``go_hispeed_load``
The CPU load at which to ramp to hispeed_freq.
Default is 99%.
``hispeed_freq``
An intermediate "high speed" at which to initially ramp
when CPU load hits the value specified in go_hispeed_load. If load
stays high for the amount of time specified in above_hispeed_delay,
then speed may be bumped higher. Default is the maximum speed allowed
by the policy at governor initialization time.
``io_is_busy``
If set, the governor accounts IO time as CPU busy time.
``min_sample_time``
The minimum amount of time to spend at the current
frequency before ramping down. Default is 80000 uS.
``target_loads``
CPU load values used to adjust speed to influence the
current CPU load toward that value. In general, the lower the target
load, the more often the governor will raise CPU speeds to bring load
below the target. The format is a single target load, optionally
followed by pairs of CPU speeds and CPU loads to target at or above
those speeds. Colons can be used between the speeds and associated
target loads for readability. For example:
85 1000000:90 1700000:99
targets CPU load 85% below speed 1GHz, 90% at or above 1GHz, until
1.7GHz and above, at which load 99% is targeted. If speeds are
specified these must appear in ascending order. Higher target load
values are typically specified for higher speeds, that is, target load
values also usually appear in an ascending order. The default is
target load 90% for all speeds.
``timer_rate``
Sample rate for reevaluating CPU load when the CPU is not
idle. A deferrable timer is used, such that the CPU will not be woken
from idle to service this timer until something else needs to run.
(The maximum time to allow deferring this timer when not running at
minimum speed is configurable via timer_slack.) Default is 20000 uS.
``timer_slack``
Maximum additional time to defer handling the governor
sampling timer beyond timer_rate when running at speeds above the
minimum. For platforms that consume additional power at idle when
CPUs are running at speeds greater than minimum, this places an upper
bound on how long the timer will be deferred prior to re-evaluating
load and dropping speed. For example, if timer_rate is 20000uS and
timer_slack is 10000uS then timers will be deferred for up to 30msec
when not at lowest speed. A value of -1 means defer timers
indefinitely at all speeds. Default is 80000 uS.
Frequency Boost Support Frequency Boost Support
======================= =======================
......
ION Memory Manager (ION)
ION is a memory manager that allows for sharing of buffers between different
processes and between user space and kernel space. ION manages different
memory spaces by separating the memory spaces into "heaps".
Required properties for Ion
- compatible: "fsl,mxc-ion"
All child nodes of a fsl,mxc-ion node are interpreted as Ion heap
configurations.
Required properties for Ion heaps
- fsl,heap-id: The ID of the ION heap.
Example:
imx_ion {
compatible = "fsl,mxc-ion";
fsl,heap-id = <0>;
};
...@@ -7,6 +7,7 @@ Required properties: ...@@ -7,6 +7,7 @@ Required properties:
- compatible : should be one of the following: - compatible : should be one of the following:
- "fsl,imx53-ahci" for i.MX53 SATA controller - "fsl,imx53-ahci" for i.MX53 SATA controller
- "fsl,imx6q-ahci" for i.MX6Q SATA controller - "fsl,imx6q-ahci" for i.MX6Q SATA controller
- "fsl,imx8qm-ahci" for i.MX8QM SATA controller
- interrupts : interrupt mapping for SATA IRQ - interrupts : interrupt mapping for SATA IRQ
- reg : registers mapping - reg : registers mapping
- clocks : list of clock specifiers, must contain an entry for each - clocks : list of clock specifiers, must contain an entry for each
...@@ -22,6 +23,9 @@ Optional properties: ...@@ -22,6 +23,9 @@ Optional properties:
for the list of legal values for these options. for the list of legal values for these options.
- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA - fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA
link. link.
- fsl,phy-imp: PHY impedance ratio value refer to the differnt HW design.
Set it to 0x6c when 85OHM is used, keep it to default value 0x80 when
100OHM is used.
Examples: Examples:
......
* Clock bindings for Freescale i.MX7ULP
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this binding doc is only for A7 clock domain.
Required properties:
- compatible: Should be "fsl,imx7ulp-scg0" or "fsl,imx7ulp-scg1".
- reg : Should contain registers location and length.
- #clock-cells: Should be <1>.
- clocks: Should contain the fixed input clocks.
- clock-name: Should contain the following clock names:"cm4_rosc",
"cm4_sosc", "cm4_sirc", "cm4_firc" for scg0.
Or
Should contain the following clock names:"rsoc", "sosc",
"sirc", "firc", "upll", "mpll" for scg1.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.
See include/dt-bindings/clock/imx7ulp-clock.h
for the full list of i.MX7ULP clock IDs.
Examples:
#include <dt-bindings/clock/imx7ulp-clock.h>
clks: scg1@403e0000 {
compatible = "fsl,imx7ulp-clock";
reg = <0x403e0000 0x10000>;
clocks = <&rsoc>, <&sosc>, <&sirc>,
<&firc>, <&upll>, <&mpll>;
clock-names = "rsoc", "sosc", "sirc",
"firc", "upll", "mpll";
#clock-cells = <1>;
};
usdhc1: usdhc@40380000 {
compatible = "fsl,imx7ulp-usdhc";
reg = <0x40380000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_USDHC1>;
clock-names ="ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
...@@ -10,7 +10,7 @@ Required properties: ...@@ -10,7 +10,7 @@ Required properties:
Example: Example:
dcp@80028000 { dcp@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>; reg = <0x80028000 0x2000>;
interrupts = <52 53>; interrupts = <52 53>;
}; };
Analog Device ADV7511(W)/13/33 HDMI Encoders Analog Device ADV7511(W)/13/33/35 HDMI Encoders
----------------------------------------- -----------------------------------------
The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video
compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space
S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while conversion, S/PDIF, CEC and HDCP. ADV7533 and ADV7535 support the DSI interface
the others support RGB interface. for input pixels, while the others support RGB interface.
Required properties: Required properties:
...@@ -13,6 +13,7 @@ Required properties: ...@@ -13,6 +13,7 @@ Required properties:
"adi,adv7511w" "adi,adv7511w"
"adi,adv7513" "adi,adv7513"
"adi,adv7533" "adi,adv7533"
"adi,adv7535"
- reg: I2C slave address - reg: I2C slave address
...@@ -46,7 +47,7 @@ The following input format properties are required except in "rgb 1x" and ...@@ -46,7 +47,7 @@ The following input format properties are required except in "rgb 1x" and
- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is - bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
needed only for ADV7511. needed only for ADV7511.
The following properties are required for ADV7533: The following properties are required for ADV7533 and ADV7535:
- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should - adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
be one of 1, 2, 3 or 4. be one of 1, 2, 3 or 4.
...@@ -65,18 +66,26 @@ Optional properties: ...@@ -65,18 +66,26 @@ Optional properties:
- adi,embedded-sync: The input uses synchronization signals embedded in the - adi,embedded-sync: The input uses synchronization signals embedded in the
data stream (similar to BT.656). Defaults to separate H/V synchronization data stream (similar to BT.656). Defaults to separate H/V synchronization
signals. signals.
- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing - adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the
generator. The chip will rely on the sync signals in the DSI data lanes, internal timing generator. The chip will rely on the sync signals in the DSI
rather than generate its own timings for HDMI output. data lanes, rather than generate its own timings for HDMI output.
- adi,dsi-channel: Only for ADV7533 and ADV7535. DSI channel number to be used
when communicating with the DSI peripheral. It should be one of 0, 1, 2 or 3.
- adi,addr-cec: Only for ADV7533 and ADV7535. The I2C DSI-CEC register map
address to be programmed into the MAIN register map.
- adi,addr-edid: Only for ADV7533 and ADV7535. The I2C EDID register map
to be programmed into the MAIN register map.
- adi,addr-pkt: Only for ADV7533 and ADV7535. The I2C PACKET register map
to be programmed into the MAIN register map.
Required nodes: Required nodes:
The ADV7511 has two video ports. Their connections are modelled using the OF The ADV7511 has two video ports. Their connections are modelled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt. graph bindings specified in Documentation/devicetree/bindings/graph.txt.
- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the - Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533 and
remote endpoint phandle should be a reference to a valid mipi_dsi_host device ADV7535, the remote endpoint phandle should be a reference to a valid
node. mipi_dsi_host device node.
- Video port 1 for the HDMI output - Video port 1 for the HDMI output
- Audio port 2 for the HDMI audio input - Audio port 2 for the HDMI audio input
......
ITE IT6263 LVDS to HDMI bridge bindings
Required properties:
- compatible: "ite,it6263"
- reg: i2c address of the bridge
- video input: this subnode can contain a video input port node
to connect the bridge to a LVDS output interface (See this
documentation [1]).
Optional properties:
- split-mode: boolean. if this exists, split mode is enabled,
otherwise, single mode is enabled.
- reset-gpios: OF device-tree gpio specification for SYSRSTN pin.
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
lvds-to-hdmi-bridge@4c {
compatible = "ite,it6263";
reg = <0x4c>;
port {
it6263_0_in: endpoint {
clock-lanes = <3>;
data-lanes = <0 1 2 4 5>;
remote-endpoint = <&lvds0_out>;
};
};
};
Northwest Logic MIPI-DSI bridge bindings
The MIPI-DSI host controller drives the video signals from
display controller to video peripherals using DSI protocol.
This is an un-managed DSI bridge. In order to use this bridge, an encoder
or bridge must be implemented to manage the platform specific initializations.
Required properties:
- compatible: "nwl,mipi-dsi"
- reg: the register range of the MIPI-DSI controller
- interrupts: the interrupt number for this module