• David Brandt's avatar
    snd: soc: fsl_sai: switch parent clock to support all bitrates in master mode · 75f4fc8a
    David Brandt authored
    The original NXP code supports clock switching in master mode only
    by setting the MCLK select bits in TCR2, but only one MCLK is ever
    defined and this is completely undocumentated in the reference manual (r0).
    Other chips using the SAI IP core (iMX6UL) only support one MCLK.
    (https://community.nxp.com/thread/442118)
    The two Audio PLLS are configured as appropriate for multiples
    of 8kHz (PLL1) and 11.05kHz (PLL2) in the iMX8MQ device trees.
    This patch adds code to switch the SAI master clock between the two
    PLLs to have valid clock ratios for all supported sample rates.
    This was deemed the best solution, other possible solutions
    included reducing supported sample rates in driver and resampling
    everything in user space (which does not work in all cases).
    There is no upstream code for this, since all NXP boards use an
    external oscillator on the bclk line.
    Tested with 8-bit, 16-bit, 32-bit Stereo, all sample rates
    up to 96kHz (limit of used codec).
    Signed-off-by: David Brandt's avatarDavid Brandt <d.brandt@phytec.de>
    Signed-off-by: default avatarChristian Hemp <c.hemp@phytec.de>
    75f4fc8a
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